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C/C++ Source or Header  |  2000-05-25  |  26KB  |  958 lines
  1. /***************************************************************************
  2.  
  3. Namco System II
  4.  
  5.   machine.c
  6.  
  7.   Functions to emulate general aspects of the machine (RAM, ROM, interrupts,
  8.   I/O ports)
  9.  
  10. ***************************************************************************/
  11.  
  12. #include "driver.h"
  13. #include "cpu/m6809/m6809.h"
  14. #include "cpu/m6805/m6805.h"
  15. #include "machine/namcos2.h"
  16. #include "vidhrdw/generic.h"
  17.  
  18. unsigned char *namcos2_68k_master_ram=NULL;
  19. unsigned char *namcos2_68k_slave_ram=NULL;
  20. unsigned char *namcos2_68k_mystery_ram=NULL;
  21.  
  22. int namcos2_gametype=0;
  23.  
  24. /*************************************************************/
  25. /* Perform basic machine initialisation                      */
  26. /*************************************************************/
  27.  
  28. void namcos2_init_machine(void)
  29. {
  30.     int loop;
  31.  
  32.     if(namcos2_dpram==NULL) namcos2_dpram = malloc(0x800);
  33.     memset( namcos2_dpram, 0, 0x800 );
  34.  
  35.     if(namcos2_sprite_ram==NULL) namcos2_sprite_ram = malloc(0x4000);
  36.     memset( namcos2_sprite_ram, 0, 0x4000 );
  37.     namcos2_sprite_bank=0;
  38.  
  39.     if(namcos2_68k_serial_comms_ram==NULL) namcos2_68k_serial_comms_ram = malloc(0x4000);
  40.     memset( namcos2_68k_serial_comms_ram, 0, 0x4000 );
  41.  
  42.     /* Initialise the bank select in the sound CPU */
  43.     namcos2_sound_bankselect_w(0,0);        /* Page in bank 0 */
  44.  
  45.     /* Place CPU2 & CPU3 into the reset condition */
  46.     namcos2_68k_master_C148_w(0x1e2000-0x1c0000,0);
  47.     namcos2_68k_master_C148_w(0x1e4000-0x1c0000,0);
  48.  
  49.     /* Initialise interrupt handlers */
  50.     for(loop=0;loop<20;loop++)
  51.     {
  52.         namcos2_68k_master_C148[loop]=0;
  53.         namcos2_68k_slave_C148[loop]=0;
  54.     }
  55.  
  56.     /* Initialise the video control registers */
  57.     for(loop=0;loop<0x40;loop+=2) namcos2_68k_vram_ctrl_w(loop,0);
  58.  
  59.     /* Initialise ROZ */
  60.     for(loop=0;loop<0x10;loop+=2) namcos2_68k_roz_ctrl_w(loop,0);
  61.  
  62.     /* Initialise the Roadway generator */
  63. //    for(loop=0;loop<0x10;loop+=2) namcos2_68k_road_ctrl_w(loop,0);
  64. }
  65.  
  66. /*************************************************************/
  67. /* EEPROM Load/Save and read/write handling                  */
  68. /*************************************************************/
  69.  
  70. unsigned char *namcos2_eeprom;
  71. size_t namcos2_eeprom_size;
  72.  
  73. void namcos2_nvram_handler(void *file,int read_or_write)
  74. {
  75.     if (read_or_write)
  76.         osd_fwrite (file, namcos2_eeprom, namcos2_eeprom_size);
  77.     else
  78.     {
  79.         if (file)
  80.             osd_fread (file, namcos2_eeprom, namcos2_eeprom_size);
  81.         else
  82.             memset (namcos2_eeprom, 0xff, namcos2_eeprom_size);
  83.     }
  84. }
  85.  
  86. WRITE_HANDLER( namcos2_68k_eeprom_w )
  87. {
  88.     int oldword = READ_WORD (&namcos2_eeprom[offset]);
  89.     int newword = COMBINE_WORD (oldword, data);
  90.     WRITE_WORD (&namcos2_eeprom[offset], newword);
  91. }
  92.  
  93. READ_HANDLER( namcos2_68k_eeprom_r )
  94. {
  95.     return READ_WORD(&namcos2_eeprom[offset]);
  96. }
  97.  
  98. /*************************************************************/
  99. /* 68000 Shared memory area - Data ROM area                  */
  100. /*************************************************************/
  101.  
  102. READ_HANDLER( namcos2_68k_data_rom_r )
  103. {
  104.     unsigned char *ROM=memory_region(REGION_USER1);
  105.     return READ_WORD(&ROM[offset]);
  106. }
  107.  
  108.  
  109. /*************************************************************/
  110. /* 68000 Shared memory area - Video RAM control              */
  111. /*************************************************************/
  112.  
  113. size_t namcos2_68k_vram_size;
  114.  
  115. WRITE_HANDLER( namcos2_68k_vram_w )
  116. {
  117. //    int col=(offset>>1)&0x3f;
  118. //    int row=(offset>>7)&0x3f;
  119.  
  120.     COMBINE_WORD_MEM(&videoram[offset],data);
  121.  
  122.     /* Some games appear to use the 409000 region as SRAM to */
  123.     /* communicate between master/slave processors ??         */
  124.  
  125.     if(offset<0x9000)
  126.     {
  127.         switch(offset&0xe000)
  128.         {
  129.             case 0x0000:
  130. //                if(namcos2_tilemap0_flip&TILEMAP_FLIPX) col=63-col;
  131. //                if(namcos2_tilemap0_flip&TILEMAP_FLIPY) row=63-row;
  132. //                tilemap_mark_tile_dirty(namcos2_tilemap0,col,row);
  133.                 tilemap_mark_tile_dirty(namcos2_tilemap0,(offset>>1)&0xfff);
  134.                 break;
  135.  
  136.             case 0x2000:
  137. //                if(namcos2_tilemap1_flip&TILEMAP_FLIPX) col=63-col;
  138. //                if(namcos2_tilemap1_flip&TILEMAP_FLIPY) row=63-row;
  139. //                tilemap_mark_tile_dirty(namcos2_tilemap1,col,row);
  140.                 tilemap_mark_tile_dirty(namcos2_tilemap1,(offset>>1)&0xfff);
  141.                 break;
  142.  
  143.             case 0x4000:
  144. //                if(namcos2_tilemap2_flip&TILEMAP_FLIPX) col=63-col;
  145. //                if(namcos2_tilemap2_flip&TILEMAP_FLIPY) row=63-row;
  146. //                tilemap_mark_tile_dirty(namcos2_tilemap2,col,row);
  147.                 tilemap_mark_tile_dirty(namcos2_tilemap2,(offset>>1)&0xfff);
  148.                 break;
  149.  
  150.             case 0x6000:
  151. //                if(namcos2_tilemap3_flip&TILEMAP_FLIPX) col=63-col;
  152. //                if(namcos2_tilemap3_flip&TILEMAP_FLIPY) row=63-row;
  153. //                tilemap_mark_tile_dirty(namcos2_tilemap3,col,row);
  154.                 tilemap_mark_tile_dirty(namcos2_tilemap3,(offset>>1)&0xfff);
  155.                 break;
  156.  
  157.             case 0x8000:
  158.                 if(offset>=0x8010 && offset<0x87f0)
  159.                 {
  160.                     offset-=0x10;    /* Fixed plane offsets */
  161. //                    row=((offset&0x7ff)>>1)/36;
  162. //                    col=((offset&0x7ff)>>1)%36;
  163. //                    if(namcos2_tilemap4_flip&TILEMAP_FLIPX) col=35-col;
  164. //                    if(namcos2_tilemap4_flip&TILEMAP_FLIPY) row=27-row;
  165. //                    tilemap_mark_tile_dirty(namcos2_tilemap4,col,row);
  166.                     tilemap_mark_tile_dirty(namcos2_tilemap4,(offset&0x7ff)>>1);
  167.                 }
  168.                 else if(offset>=0x8810 && offset<0x8ff0)
  169.                 {
  170.                     offset-=0x10;    /* Fixed plane offsets */
  171. //                    row=((offset&0x7ff)>>1)/36;
  172. //                    col=((offset&0x7ff)>>1)%36;
  173. //                    if(namcos2_tilemap5_flip&TILEMAP_FLIPX) col=35-col;
  174. //                    if(namcos2_tilemap5_flip&TILEMAP_FLIPY) row=27-row;
  175. //                    tilemap_mark_tile_dirty(namcos2_tilemap5,col,row);
  176.                     tilemap_mark_tile_dirty(namcos2_tilemap5,(offset&0x7ff)>>1);
  177.                 }
  178.                 break;
  179.  
  180.             default:
  181.                 break;
  182.         }
  183.     }
  184. }
  185.  
  186. READ_HANDLER( namcos2_68k_vram_r )
  187. {
  188.     int data=READ_WORD(&videoram[offset]);
  189.     return data;
  190. }
  191.  
  192.  
  193.  
  194. unsigned char namcos2_68k_vram_ctrl[0x40];
  195.  
  196. WRITE_HANDLER( namcos2_68k_vram_ctrl_w )
  197. {
  198.     int olddata=namcos2_68k_vram_ctrl_r(offset&0x3f)&0x0f;
  199.     int newdata=data&0x0f;
  200.     int flip;
  201.  
  202.     /* Write word to register */
  203.     COMBINE_WORD_MEM(&namcos2_68k_vram_ctrl[offset&0x3f],data);
  204.  
  205.     switch(offset&0x3f)
  206.     {
  207.         case 0x02:
  208.             /* All planes are flipped X+Y from D15 of this word */
  209.             flip=(namcos2_68k_vram_ctrl_r(0x02)&0x8000)?(TILEMAP_FLIPX|TILEMAP_FLIPY):0;
  210.             if(namcos2_tilemap0_flip!=flip) tilemap_mark_all_tiles_dirty(ALL_TILEMAPS);
  211.  
  212.             tilemap_set_flip( ALL_TILEMAPS, flip );
  213. //            namcos2_tilemap0_flip=flip;
  214. //            namcos2_tilemap1_flip=flip;
  215. //            namcos2_tilemap2_flip=flip;
  216. //            namcos2_tilemap3_flip=flip;
  217. //            namcos2_tilemap4_flip=flip;
  218. //            namcos2_tilemap5_flip=flip;
  219.  
  220.             tilemap_set_scrollx( namcos2_tilemap0, 0, (data+44+4)&0x1ff );
  221.             break;
  222.         case 0x06:
  223.             tilemap_set_scrolly( namcos2_tilemap0, 0, (data+24)&0x1ff );
  224.             break;
  225.         case 0x0a:
  226.             tilemap_set_scrollx( namcos2_tilemap1, 0, (data+44+2)&0x1ff );
  227.             break;
  228.         case 0x0e:
  229.             tilemap_set_scrolly( namcos2_tilemap1, 0, (data+24)&0x1ff );
  230.             break;
  231.         case 0x12:
  232.             tilemap_set_scrollx( namcos2_tilemap2, 0, (data+44+1)&0x1ff );
  233.             break;
  234.         case 0x16:
  235.             tilemap_set_scrolly( namcos2_tilemap2, 0, (data+24)&0x1ff );
  236.             break;
  237.         case 0x1a:
  238.             tilemap_set_scrollx( namcos2_tilemap3, 0, (data+44)&0x1ff );
  239.             break;
  240.         case 0x1e:
  241.             tilemap_set_scrolly( namcos2_tilemap3, 0, (data+24)&0x1ff );
  242.             break;
  243.         case 0x30:
  244.             /* Change of colour bank needs to force a tilemap redraw */
  245.             if(newdata!=olddata) tilemap_mark_all_tiles_dirty(namcos2_tilemap0);
  246.             break;
  247.         case 0x32:
  248.             /* Change of colour bank needs to force a tilemap redraw */
  249.             if(newdata!=olddata) tilemap_mark_all_tiles_dirty(namcos2_tilemap1);
  250.             break;
  251.         case 0x34:
  252.             /* Change of colour bank needs to force a tilemap redraw */
  253.             if(newdata!=olddata) tilemap_mark_all_tiles_dirty(namcos2_tilemap2);
  254.             break;
  255.         case 0x36:
  256.             /* Change of colour bank needs to force a tilemap redraw */
  257.             if(newdata!=olddata) tilemap_mark_all_tiles_dirty(namcos2_tilemap3);
  258.             break;
  259.         case 0x38:
  260.             /* Change of colour bank needs to force a tilemap redraw */
  261.             if(newdata!=olddata) tilemap_mark_all_tiles_dirty(namcos2_tilemap4);
  262.             break;
  263.         case 0x3a:
  264.             /* Change of colour bank needs to force a tilemap redraw */
  265.             if(newdata!=olddata) tilemap_mark_all_tiles_dirty(namcos2_tilemap5);
  266.             break;
  267.         default:
  268.             break;
  269.     }
  270. }
  271.  
  272. READ_HANDLER( namcos2_68k_vram_ctrl_r )
  273. {
  274.     return READ_WORD(&namcos2_68k_vram_ctrl[offset&0x3f]);
  275. }
  276.  
  277.  
  278. /*************************************************************/
  279. /* 68000 Shared memory area - Video palette control          */
  280. /*************************************************************/
  281.  
  282. unsigned char *namcos2_68k_palette_ram;
  283. size_t namcos2_68k_palette_size;
  284.  
  285. READ_HANDLER( namcos2_68k_video_palette_r )
  286. {
  287.     if((offset&0xf000)==0x3000)
  288.     {
  289.         /* Palette chip control registers */
  290.         offset&=0x001f;
  291.         switch(offset)
  292.         {
  293.             case 0x1a:
  294.             case 0x1e:
  295.                 return 0xff;
  296.                 break;
  297.             default:
  298.                 break;
  299.         }
  300.     }
  301.     return READ_WORD(&namcos2_68k_palette_ram[offset&0xffff]);
  302. }
  303.  
  304. WRITE_HANDLER( namcos2_68k_video_palette_w )
  305. {
  306.     int oldword = READ_WORD(&namcos2_68k_palette_ram[offset&0xffff]);
  307.     int newword = COMBINE_WORD(oldword, data);
  308.     int pen,red,green,blue;
  309.  
  310.     if(oldword != newword)
  311.     {
  312.         WRITE_WORD(&namcos2_68k_palette_ram[offset&0xffff],newword);
  313.  
  314.         /* 0x3000 offset is control registers */
  315.         if((offset&0x3000)!=0x3000)
  316.         {
  317.             pen=(((offset&0xc000)>>2) | (offset&0x0fff))>>1;
  318.  
  319.             red  =(READ_WORD(&namcos2_68k_palette_ram[offset&0xcfff]))&0x00ff;
  320.             green=(READ_WORD(&namcos2_68k_palette_ram[(offset&0xcfff)+0x1000]))&0x00ff;
  321.             blue =(READ_WORD(&namcos2_68k_palette_ram[(offset&0xcfff)+0x2000]))&0x00ff;
  322.  
  323.             palette_change_color(pen,red,green,blue);
  324.         }
  325.     }
  326. }
  327.  
  328. /*************************************************************/
  329. /* 68000/6809/63705 Shared memory area - DUAL PORT Memory     */
  330. /*************************************************************/
  331.  
  332. unsigned char *namcos2_dpram=NULL;    /* 2Kx8 */
  333.  
  334. READ_HANDLER( namcos2_68k_dpram_word_r )
  335. {
  336.     offset = offset/2;
  337.     return namcos2_dpram[offset&0x7ff];
  338. }
  339.  
  340. WRITE_HANDLER( namcos2_68k_dpram_word_w )
  341. {
  342.     offset = offset/2;
  343.     if(!(data & 0x00ff0000)) namcos2_dpram[offset&0x7ff] = data & 0xff;
  344. }
  345.  
  346. READ_HANDLER( namcos2_dpram_byte_r )
  347. {
  348.     return namcos2_dpram[offset&0x7ff];
  349. }
  350.  
  351. WRITE_HANDLER( namcos2_dpram_byte_w )
  352. {
  353.     namcos2_dpram[offset&0x7ff] = data;
  354. }
  355.  
  356.  
  357. /**************************************************************/
  358. /* 68000 Shared serial communications processor (CPU5?)       */
  359. /**************************************************************/
  360.  
  361. unsigned char  namcos2_68k_serial_comms_ctrl[0x10];
  362. unsigned char *namcos2_68k_serial_comms_ram=NULL;
  363.  
  364. READ_HANDLER( namcos2_68k_serial_comms_ram_r )
  365. {
  366.     logerror("Serial Comms read  Addr=%08x\n",offset);
  367.     return READ_WORD(&namcos2_68k_serial_comms_ram[offset&0x3fff]);
  368. }
  369.  
  370. WRITE_HANDLER( namcos2_68k_serial_comms_ram_w )
  371. {
  372.     COMBINE_WORD_MEM(&namcos2_68k_serial_comms_ram[offset&0x3fff],data&0x1ff);
  373.     logerror("Serial Comms write Addr=%08x, Data=%04x\n",offset,data);
  374. }
  375.  
  376.  
  377. READ_HANDLER( namcos2_68k_serial_comms_ctrl_r )
  378. {
  379.     int retval=READ_WORD(&namcos2_68k_serial_comms_ctrl[offset&0x0f]);
  380.  
  381.     switch(offset)
  382.     {
  383.         case 0x00:
  384.             retval|=0x0004;     /* Set READY? status bit */
  385.             break;
  386.         default:
  387.             break;
  388.     }
  389. //    logerror("Serial Comms read  Addr=%08x\n",offset);
  390.  
  391.     return retval;
  392. }
  393.  
  394. WRITE_HANDLER( namcos2_68k_serial_comms_ctrl_w )
  395. {
  396.     COMBINE_WORD_MEM(&namcos2_68k_serial_comms_ctrl[offset&0x0f],data);
  397. //    logerror("Serial Comms write Addr=%08x, Data=%04x\n",offset,data);
  398. }
  399.  
  400.  
  401.  
  402. /*************************************************************/
  403. /* 68000 Shared SPRITE/OBJECT Memory access/control          */
  404. /*************************************************************/
  405.  
  406. /* The sprite bank register also holds the colour bank for */
  407. /* the ROZ memory and some of the priority control data    */
  408.  
  409. unsigned char *namcos2_sprite_ram=NULL;
  410. int namcos2_sprite_bank=0;
  411.  
  412. WRITE_HANDLER( namcos2_68k_sprite_ram_w )
  413. {
  414.     COMBINE_WORD_MEM(&namcos2_sprite_ram[offset&0x3fff],data);
  415. }
  416.  
  417. WRITE_HANDLER( namcos2_68k_sprite_bank_w )
  418. {
  419.     int newword = COMBINE_WORD(namcos2_sprite_bank, data);
  420.     namcos2_sprite_bank=newword;
  421. }
  422.  
  423. READ_HANDLER( namcos2_68k_sprite_ram_r )
  424. {
  425.     int data=READ_WORD(&namcos2_sprite_ram[offset&0x3fff]);
  426.     return data;
  427. }
  428.  
  429. READ_HANDLER( namcos2_68k_sprite_bank_r )
  430. {
  431.     return namcos2_sprite_bank;
  432. }
  433.  
  434.  
  435.  
  436. /*************************************************************/
  437. /* 68000 Shared protection/random key generator              */
  438. /*************************************************************/
  439. //
  440. //$d00000
  441. //$d00002
  442. //$d00004      Write 13 x $0000, read back $00bd from $d00002 (burnf)
  443. //$d00006      Write $b929, read $014a (cosmog, does a jmp $0 if it doesnt get this)
  444. //$d00008      Write $13ec, read $013f (rthun2)
  445. //$d0000a      Write $f00f, read $f00f (phelios)
  446. //$d0000c      Write $8fc8, read $00b2 (rthun2)
  447. //$d0000e      Write $31ad, read $00bd (burnf)
  448. //
  449.  
  450. unsigned char namcos2_68k_key[0x10];
  451.  
  452. READ_HANDLER( namcos2_68k_key_r )
  453. {
  454. /*    return READ_WORD(&namcos2_68k_key[offset&0x0f]); */
  455.     return rand()&0xffff;
  456. }
  457.  
  458. WRITE_HANDLER( namcos2_68k_key_w )
  459. {
  460.     /* Seed the random number generator */
  461.     srand(data);
  462.     COMBINE_WORD_MEM(&namcos2_68k_key[offset&0x0f],data);
  463. }
  464.  
  465.  
  466. /**************************************************************/
  467. /*    ROZ - Rotate & Zoom memory function handlers              */
  468. /*                                                              */
  469. /*    ROZ control made up of 8 registers, looks to be split      */
  470. /*    into 2 groups of 3 registers one for each plane and two   */
  471. /*    other registers ??                                          */
  472. /*                                                              */
  473. /*    0 - Plane 2 Offset 0x20000                                  */
  474. /*    2 - Plane 2                                               */
  475. /*    4 - Plane 2                                               */
  476. /*    6 - Plane 1 Offset 0x00000                                  */
  477. /*    8 - Plane 1                                               */
  478. /*    A    Plane 1                                               */
  479. /*    C - Unused                                                  */
  480. /*    E - Control reg ??                                          */
  481. /*                                                              */
  482. /**************************************************************/
  483.  
  484. unsigned char namcos2_68k_roz_ctrl[0x10];
  485. size_t namcos2_68k_roz_ram_size;
  486. unsigned char *namcos2_68k_roz_ram=NULL;
  487.  
  488. WRITE_HANDLER( namcos2_68k_roz_ctrl_w )
  489. {
  490.     COMBINE_WORD_MEM(&namcos2_68k_roz_ctrl[offset&0x0f],data);
  491. }
  492.  
  493. READ_HANDLER( namcos2_68k_roz_ctrl_r )
  494. {
  495.     return READ_WORD(&namcos2_68k_roz_ctrl[offset&0x0f]);
  496. }
  497.  
  498. WRITE_HANDLER( namcos2_68k_roz_ram_w )
  499. {
  500.     COMBINE_WORD_MEM(&namcos2_68k_roz_ram[offset],data);
  501. }
  502.  
  503. READ_HANDLER( namcos2_68k_roz_ram_r )
  504. {
  505.     return READ_WORD(&namcos2_68k_roz_ram[offset]);
  506. }
  507.  
  508.  
  509.  
  510. /**************************************************************/
  511. /*                                                              */
  512. /*    Final Lap 1/2/3 Roadway generator function handlers       */
  513. /*                                                              */
  514. /**************************************************************/
  515.  
  516. unsigned char *namcos2_68k_roadtile_ram=NULL;
  517. unsigned char *namcos2_68k_roadgfx_ram=NULL;
  518. size_t namcos2_68k_roadtile_ram_size;
  519. size_t namcos2_68k_roadgfx_ram_size;
  520.  
  521. WRITE_HANDLER( namcos2_68k_roadtile_ram_w )
  522. {
  523.     COMBINE_WORD_MEM(&namcos2_68k_roadtile_ram[offset],data);
  524. }
  525.  
  526. READ_HANDLER( namcos2_68k_roadtile_ram_r )
  527. {
  528.     return READ_WORD(&namcos2_68k_roadtile_ram[offset]);
  529. }
  530.  
  531. WRITE_HANDLER( namcos2_68k_roadgfx_ram_w )
  532. {
  533.     COMBINE_WORD_MEM(&namcos2_68k_roadgfx_ram[offset],data);
  534. }
  535.  
  536. READ_HANDLER( namcos2_68k_roadgfx_ram_r )
  537. {
  538.     return READ_WORD(&namcos2_68k_roadgfx_ram[offset]);
  539. }
  540.  
  541. WRITE_HANDLER( namcos2_68k_road_ctrl_w )
  542. {
  543. }
  544.  
  545. READ_HANDLER( namcos2_68k_road_ctrl_r )
  546. {
  547.     return 0;
  548. }
  549.  
  550.  
  551. /*************************************************************/
  552. /* 68000 Interrupt/IO Handlers - CUSTOM 148 - NOT SHARED     */
  553. /*************************************************************/
  554.  
  555. #define NO_OF_LINES     256
  556. #define FRAME_TIME        (1.0/60.0)
  557. #define LINE_LENGTH     (FRAME_TIME/NO_OF_LINES)
  558.  
  559. int  namcos2_68k_master_C148[0x20];
  560. int  namcos2_68k_slave_C148[0x20];
  561.  
  562. WRITE_HANDLER( namcos2_68k_master_C148_w )
  563. {
  564.     offset+=0x1c0000;
  565.     offset&=0x1fe000;
  566.  
  567.     data&=0x0007;
  568.     namcos2_68k_master_C148[(offset>>13)&0x1f]=data;
  569.  
  570.     switch(offset)
  571.     {
  572.         case 0x1d4000:
  573.             /* Trigger Master to Slave interrupt */
  574. //            cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
  575.             break;
  576.         case 0x1d6000:
  577.             /* Clear Slave to Master*/
  578. //            cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
  579.             break;
  580.         case 0x1de000:
  581.             cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
  582.             break;
  583.         case 0x1da000:
  584.             cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
  585.             break;
  586.  
  587.         case 0x1e2000:                /* Reset register CPU3 */
  588.             {
  589.                 data&=0x01;
  590.                 if(data&0x01)
  591.                 {
  592.                     /* Resume execution */
  593.                     cpu_set_reset_line (NAMCOS2_CPU3, CLEAR_LINE);
  594.                     cpu_yield();
  595.                 }
  596.                 else
  597.                 {
  598.                     /* Suspend execution */
  599.                     cpu_set_reset_line(NAMCOS2_CPU3, ASSERT_LINE);
  600.                 }
  601.             }
  602.             break;
  603.         case 0x1e4000:                /* Reset register CPU2 & CPU4 */
  604.             {
  605.                 data&=0x01;
  606.                 if(data&0x01)
  607.                 {
  608.                     /* Resume execution */
  609.                     cpu_set_reset_line(NAMCOS2_CPU2, CLEAR_LINE);
  610.                     cpu_set_reset_line(NAMCOS2_CPU4, CLEAR_LINE);
  611.                     /* Give the new CPU an immediate slice of the action */
  612.                     cpu_yield();
  613.                 }
  614.                 else
  615.                 {
  616.                     /* Suspend execution */
  617.                     cpu_set_reset_line(NAMCOS2_CPU2, ASSERT_LINE);
  618.                     cpu_set_reset_line(NAMCOS2_CPU4, ASSERT_LINE);
  619.                 }
  620.             }
  621.             break;
  622.         case 0x1e6000:                    /* Watchdog reset */
  623.             /* watchdog_reset_w(0,0); */
  624.             break;
  625.         default:
  626.             break;
  627.     }
  628. }
  629.  
  630.  
  631. READ_HANDLER( namcos2_68k_master_C148_r )
  632. {
  633.     offset+=0x1c0000;
  634.     offset&=0x1fe000;
  635.  
  636.     switch(offset)
  637.     {
  638.         case 0x1d6000:
  639.             /* Clear Slave to Master*/
  640. //            cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
  641.             break;
  642.         case 0x1de000:
  643.             cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
  644.             break;
  645.         case 0x1da000:
  646.             cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
  647.             break;
  648.         case 0x1e0000:                    /* EEPROM Status register*/
  649.             return 0xffff;                /* Only BIT0 used: 1=EEPROM READY 0=EEPROM BUSY */
  650.             break;
  651.         case 0x1e6000:                    /* Watchdog reset */
  652.             /* watchdog_reset_w(0,0); */
  653.             break;
  654.         default:
  655.             break;
  656.     }
  657.     return namcos2_68k_master_C148[(offset>>13)&0x1f];
  658. }
  659.  
  660. int namcos2_68k_master_vblank(void)
  661. {
  662.     /* If the POS interrupt is running then set it at half way thru the frame */
  663.     if(namcos2_68k_master_C148[NAMCOS2_C148_POSIRQ])
  664.     {
  665.         timer_set(TIME_IN_NSEC(LINE_LENGTH*100), 0, namcos2_68k_master_posirq);
  666.     }
  667.  
  668.     /* Assert the VBLANK interrupt */
  669.     return namcos2_68k_master_C148[NAMCOS2_C148_VBLANKIRQ];
  670. }
  671.  
  672. void namcos2_68k_master_posirq( int moog )
  673. {
  674.     cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_POSIRQ], ASSERT_LINE);
  675.     cpu_set_irq_line(CPU_SLAVE , namcos2_68k_slave_C148[NAMCOS2_C148_POSIRQ] , ASSERT_LINE);
  676. }
  677.  
  678.  
  679. WRITE_HANDLER( namcos2_68k_slave_C148_w )
  680. {
  681.     offset+=0x1c0000;
  682.     offset&=0x1fe000;
  683.  
  684.     data&=0x0007;
  685.     namcos2_68k_slave_C148[(offset>>13)&0x1f]=data;
  686.  
  687.     switch(offset)
  688.     {
  689.         case 0x1d4000:
  690.             /* Trigger Slave to Master interrupt */
  691. //            cpu_set_irq_line(CPU_MASTER, namcos2_68k_master_C148[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
  692.             break;
  693.         case 0x1d6000:
  694.             /* Clear Master to Slave */
  695. //            cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
  696.             break;
  697.         case 0x1de000:
  698.             cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
  699.             break;
  700.         case 0x1da000:
  701.             cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
  702.             break;
  703.         case 0x1e6000:                    /* Watchdog reset */
  704.             /* watchdog_reset_w(0,0); */
  705.             break;
  706.         default:
  707.             break;
  708.     }
  709. }
  710.  
  711.  
  712. READ_HANDLER( namcos2_68k_slave_C148_r )
  713. {
  714.     offset+=0x1c0000;
  715.     offset&=0x1fe000;
  716.  
  717.     switch(offset)
  718.     {
  719.         case 0x1d6000:
  720.             /* Clear Master to Slave */
  721. //            cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
  722.             break;
  723.         case 0x1de000:
  724.             cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
  725.             break;
  726.         case 0x1da000:
  727.             cpu_set_irq_line(CPU_SLAVE, namcos2_68k_slave_C148[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
  728.             break;
  729.         case 0x1e6000:                    /* Watchdog reset */
  730.             /* watchdog_reset_w(0,0); */
  731.             break;
  732.         default:
  733.             break;
  734.     }
  735.     return namcos2_68k_slave_C148[(offset>>13)&0x1f];
  736. }
  737.  
  738. int namcos2_68k_slave_vblank(void)
  739. {
  740.     return namcos2_68k_slave_C148[NAMCOS2_C148_VBLANKIRQ];
  741. }
  742.  
  743. /**************************************************************/
  744. /*    Sound sub-system                                          */
  745. /**************************************************************/
  746.  
  747. int namcos2_sound_interrupt(void)
  748. {
  749.     return M6809_INT_FIRQ;
  750. }
  751.  
  752.  
  753. WRITE_HANDLER( namcos2_sound_bankselect_w )
  754. {
  755.     unsigned char *RAM=memory_region(REGION_CPU3);
  756.     int bank = ( data >> 4 ) & 0x0f;    /* 991104.CAB */
  757.     cpu_setbank( CPU3_ROM1, &RAM[ 0x10000 + ( 0x4000 * bank ) ] );
  758. }
  759.  
  760.  
  761.  
  762. /**************************************************************/
  763. /*                                                              */
  764. /*    68705 IO CPU Support functions                              */
  765. /*                                                              */
  766. /**************************************************************/
  767.  
  768. int namcos2_mcu_interrupt(void)
  769. {
  770.     return HD63705_INT_IRQ;
  771. }
  772.  
  773. static int namcos2_mcu_analog_ctrl=0;
  774. static int namcos2_mcu_analog_data=0xaa;
  775. static int namcos2_mcu_analog_complete=0;
  776.  
  777. WRITE_HANDLER( namcos2_mcu_analog_ctrl_w )
  778. {
  779.     namcos2_mcu_analog_ctrl=data&0xff;
  780.  
  781.     /* Check if this is a start of conversion */
  782.     /* Input ports 2 thru 9 are the analog channels */
  783.     if(data&0x40)
  784.     {
  785.         /* Set the conversion complete flag */
  786.         namcos2_mcu_analog_complete=2;
  787.         /* We convert instantly, good eh! */
  788.         switch((data>>2)&0x07)
  789.         {
  790.             case 0:
  791.                 namcos2_mcu_analog_data=input_port_2_r(0);
  792.                 break;
  793.             case 1:
  794.                 namcos2_mcu_analog_data=input_port_3_r(0);
  795.                 break;
  796.             case 2:
  797.                 namcos2_mcu_analog_data=input_port_4_r(0);
  798.                 break;
  799.             case 3:
  800.                 namcos2_mcu_analog_data=input_port_5_r(0);
  801.                 break;
  802.             case 4:
  803.                 namcos2_mcu_analog_data=input_port_6_r(0);
  804.                 break;
  805.             case 5:
  806.                 namcos2_mcu_analog_data=input_port_7_r(0);
  807.                 break;
  808.             case 6:
  809.                 namcos2_mcu_analog_data=input_port_8_r(0);
  810.                 break;
  811.             case 7:
  812.                 namcos2_mcu_analog_data=input_port_9_r(0);
  813.                 break;
  814.         }
  815. #if 0
  816.         /* Perform the offset handling on the input port */
  817.         /* this converts it to a twos complement number */
  818.         if ((namcos2_gametype==NAMCOS2_DIRT_FOX) ||
  819.             (namcos2_gametype==NAMCOS2_DIRT_FOX_JP))
  820.         namcos2_mcu_analog_data^=0x80;
  821. #endif
  822.  
  823.         /* If the interrupt enable bit is set trigger an A/D IRQ */
  824.         if(data&0x20)
  825.         {
  826.             cpu_set_irq_line( CPU_MCU, HD63705_INT_ADCONV , PULSE_LINE);
  827.         }
  828.     }
  829. }
  830.  
  831. READ_HANDLER( namcos2_mcu_analog_ctrl_r )
  832. {
  833.     int data=0;
  834.  
  835.     /* ADEF flag is only cleared AFTER a read from control THEN a read from DATA */
  836.     if(namcos2_mcu_analog_complete==2) namcos2_mcu_analog_complete=1;
  837.     if(namcos2_mcu_analog_complete) data|=0x80;
  838.  
  839.     /* Mask on the lower 6 register bits, Irq EN/Channel/Clock */
  840.     data|=namcos2_mcu_analog_ctrl&0x3f;
  841.     /* Return the value */
  842.     return data;
  843. }
  844.  
  845. WRITE_HANDLER( namcos2_mcu_analog_port_w )
  846. {
  847. }
  848.  
  849. READ_HANDLER( namcos2_mcu_analog_port_r )
  850. {
  851.     if(namcos2_mcu_analog_complete==1) namcos2_mcu_analog_complete=0;
  852.     return namcos2_mcu_analog_data;
  853. }
  854.  
  855. WRITE_HANDLER( namcos2_mcu_port_d_w )
  856. {
  857.     /* Undefined operation on write */
  858. }
  859.  
  860. READ_HANDLER( namcos2_mcu_port_d_r )
  861. {
  862.     /* Provides a digital version of the analog ports */
  863.     int threshold=0x7f;
  864.     int data=0;
  865.  
  866.     /* Read/convert the bits one at a time */
  867.     if(input_port_2_r(0)>threshold) data|=0x01;
  868.     if(input_port_3_r(0)>threshold) data|=0x02;
  869.     if(input_port_4_r(0)>threshold) data|=0x04;
  870.     if(input_port_5_r(0)>threshold) data|=0x08;
  871.     if(input_port_6_r(0)>threshold) data|=0x10;
  872.     if(input_port_7_r(0)>threshold) data|=0x20;
  873.     if(input_port_8_r(0)>threshold) data|=0x40;
  874.     if(input_port_9_r(0)>threshold) data|=0x80;
  875.  
  876.     /* Return the result */
  877.     return data;
  878. }
  879.  
  880. READ_HANDLER( namcos2_input_port_0_r )
  881. {
  882.     int data=readinputport(0);
  883.  
  884.     int one_joy_trans0[2][10]={
  885.         {0x05,0x01,0x09,0x08,0x0a,0x02,0x06,0x04,0x12,0x14},
  886.         {0x00,0x20,0x20,0x20,0x08,0x08,0x00,0x08,0x02,0x02}};
  887.  
  888.     int datafake, i;
  889.  
  890.     switch(namcos2_gametype)
  891.     {
  892.         case NAMCOS2_ASSAULT:
  893.         case NAMCOS2_ASSAULT_JP:
  894.         case NAMCOS2_ASSAULT_PLUS:
  895.             datafake=~readinputport(15) & 0xff;
  896.             logerror("xxx=%08x\n",datafake);
  897.             for (i=0;i<10;i++)
  898.                 if (datafake==one_joy_trans0[0][i])
  899.                 {
  900.                     data&=~one_joy_trans0[1][i];
  901.                     break;
  902.                 }
  903.     }
  904.     return data;
  905. }
  906.  
  907. READ_HANDLER( namcos2_input_port_10_r )
  908. {
  909.     int data=readinputport(10);
  910.  
  911.     int one_joy_trans10[2][10]={
  912.         {0x05,0x01,0x09,0x08,0x0a,0x02,0x06,0x04,0x1a,0x18},
  913.         {0x08,0x08,0x00,0x02,0x00,0x02,0x02,0x08,0x80,0x80}};
  914.  
  915.     int datafake, i;
  916.  
  917.     switch(namcos2_gametype)
  918.     {
  919.         case NAMCOS2_ASSAULT:
  920.         case NAMCOS2_ASSAULT_JP:
  921.         case NAMCOS2_ASSAULT_PLUS:
  922.             datafake=~readinputport(15) & 0xff;
  923.             for (i=0;i<10;i++)
  924.                 if (datafake==one_joy_trans10[0][i])
  925.                 {
  926.                     data&=~one_joy_trans10[1][i];
  927.                     break;
  928.                 }
  929.     }
  930.     return data;
  931. }
  932.  
  933. READ_HANDLER( namcos2_input_port_12_r )
  934. {
  935.     int data=readinputport(12);
  936.  
  937.     int one_joy_trans12[2][4]={
  938.         {0x12,0x14,0x11,0x18},
  939.         {0x02,0x08,0x08,0x02}};
  940.  
  941.     int datafake, i;
  942.  
  943.     switch(namcos2_gametype)
  944.     {
  945.         case NAMCOS2_ASSAULT:
  946.         case NAMCOS2_ASSAULT_JP:
  947.         case NAMCOS2_ASSAULT_PLUS:
  948.             datafake=~readinputport(15) & 0xff;
  949.             for (i=0;i<4;i++)
  950.                 if (datafake==one_joy_trans12[0][i])
  951.                 {
  952.                     data&=~one_joy_trans12[1][i];
  953.                     break;
  954.                 }
  955.     }
  956.     return data;
  957. }
  958.